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I think I have discovered a bug in or1k’s simulation of the 16450 UART with respect to transmit interrupts. ( I noticed this when I switched from polling mode to interrupt-driven transmit using eCos’ serial drivers.)
The UART is supposed to raise an interrupt whenever its THR (Transmit Head Register) and transmit FIFO are both empty and transmit interrupts are enabled. That is, an interrupt should be raised whenever the THRE (THR empty) bit is asserted in the LSR register. However, there is some UART state machine logic that disables that interrupt until at least one character has been written to the THR and transferred to the transmit FIFO, even if THRE is asserted. In the case of a driver that waits for a THRE interrupt before writing characters to the THR, no characters will ever be transmitted.
According to CVS, Marko wrote those sections of the state machine (or at least, he checked them in). Marko, do you have any insight as to why this code was added ?
Attached is my proposed patch, which doesn’t add any code; It just removes a small section of the UART state machine.
-Scott
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