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Re: [openrisc] generic flip-flop based memories.

To: openrisc@opencores.org
Subject: Re: [openrisc] generic flip-flop based memories.
From: Christian Melki <christian.melki@axis.com>
Date: Thu, 27 Mar 2003 10:35:21 +0100 (CET)
cc: lampret@opencores.org
In-Reply-To: <03cb01c2f423$ae7f3480$ed01ed0a@flextronics.si>
Reply-To: openrisc@opencores.org
Sender: owner-openrisc@opencores.org

Hi,

I don't have them as hard macros.. I don't think I have the time
( or skills yet ) to design my own hard macro. I have however written
a .tlf which is supposed to model some "timing" of the memory types in the
design. Ok, its probably never as good as a hard macro.. but this is
currently my only way of defining the memcells in a timing sense at least.
If you find the time.. could you please look at the .tlf included and
give me a comment about setup, hold and path-timings from clk->do.

About the MAC/mult:
ok. its there to be balanced by a synth tool.. but are they intelligent
enough to understand this? does DC do a good job of balancing the two
stages?
True.. sometimes it is in the critical path. But that depends. If you
don't have balanced work between the stages.. your still going to
break it with the weakest link in the chain.
the ASIC mult is still to complex for me to follow in such a low level
form.( im still new to this.. :). so i can't make a judgement on how
balanced it is.. we did however do som separate synthesis on it.. and
it seems to be chewing data happily at 400MHz. ( very speculative. i
didn't do the tests.. and they are not finished yet. )

regards
/Christian

On Wed, 26 Mar 2003, Damjan Lampret wrote:

> Christian,
>
> I don't think it makes sense to have them flop (or latch) based (except of
> you don't have them as hard macros and can't generate them) since they will
> be slower and bigger. What I'd do if I wouldn't have memory compilers, I'd
> design a latch based hard macro and use it instead of any currently
> supported hard macro memories.
>
> Yes you are right, the second stage is to have it balanced by synthesis
> tool.
>
> MAC in two stages. Yes probably, it depends what kind of libraries and
> process you use. In some cases critical path can be the multiplier stage of
> the MAC.
>
> regards,
> Damjan

Header(
	Library("memcells")
	TLF_Version("4.3")
	Generated_By("CM")
)

Cell(timing_tpram_32x32
	PIN(clk_a
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	PIN(clk_b
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	
	BUS(addr_a[4:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(addr_b[4:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di_a[31:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di_b[31:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do_a[31:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	BUS(do_b[31:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we_a
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PIN(we_b
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk_a *> do_a[31:0] 01 01
		Delay((Const (2.0)))
		Slew((Const(0.3))))
	PATH(clk_a *> do_a[31:0] 01 10
		Delay((Const (2.0)))
		Slew((Const(0.3))))
	PATH(clk_b *> do_b[31:0] 01 01
		Delay((Const (2.0)))
		Slew((Const(0.3))))
	PATH(clk_b *> do_b[31:0] 01 10
		Delay((Const (2.0)))
		Slew((Const(0.3))))

	SETUP(addr_a[4:0] *> clk_a 01 Posedge (Const(1.0)))
	SETUP(addr_a[4:0] *> clk_a 10 Posedge (Const(1.0)))
	SETUP(addr_b[4:0] *> clk_b 01 Posedge (Const(1.0)))
	SETUP(addr_b[4:0] *> clk_b 10 Posedge (Const(1.0)))
	SETUP(di_a[31:0] *> clk_a 01 Posedge (Const(0.5)))
	SETUP(di_a[31:0] *> clk_a 10 Posedge (Const(0.5)))
	SETUP(di_b[31:0] *> clk_b 01 Posedge (Const(0.5)))
	SETUP(di_b[31:0] *> clk_b 10 Posedge (Const(0.5)))
	SETUP(we_a *> clk_a 01 Posedge (Const(0.5)))
	SETUP(we_a *> clk_a 10 Posedge (Const(0.5)))
	SETUP(we_b *> clk_b 01 Posedge (Const(0.5)))
	SETUP(we_b *> clk_b 10 Posedge (Const(0.5)))

	HOLD(addr_a[4:0] *> clk_a 01 Posedge (Const(0.5)))
	HOLD(addr_a[4:0] *> clk_a 10 Posedge (Const(0.5)))
	HOLD(addr_b[4:0] *> clk_b 01 Posedge (Const(0.5)))
	HOLD(addr_b[4:0] *> clk_b 10 Posedge (Const(0.5)))
	HOLD(di_a[31:0] *> clk_a 01 Posedge (Const(0.5)))
	HOLD(di_a[31:0] *> clk_a 10 Posedge (Const(0.5)))
	HOLD(di_b[31:0] *> clk_b 01 Posedge (Const(0.5)))
	HOLD(di_b[31:0] *> clk_b 10 Posedge (Const(0.5)))
	HOLD(we_a *> clk_a 01 Posedge (Const(0.5)))
	HOLD(we_a *> clk_a 10 Posedge (Const(0.5)))
	HOLD(we_b *> clk_b 01 Posedge (Const(0.5)))
	HOLD(we_b *> clk_b 10 Posedge (Const(0.5)))
)

Cell(timing_dpram_32x32
	PIN(clk_a
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	PIN(clk_b
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	
	BUS(addr_a[4:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(addr_b[4:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di_b[31:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do_a[31:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we_b
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk_a *> do_a[31:0] 01 01
		Delay((Const (2.0)))
		Slew((Const(0.3))))
	PATH(clk_a *> do_a[31:0] 01 10
		Delay((Const (2.0)))
		Slew((Const(0.3))))

	SETUP(addr_a[4:0] *> clk_a 01 Posedge (Const(1.0)))
	SETUP(addr_a[4:0] *> clk_a 10 Posedge (Const(1.0)))
	SETUP(addr_b[4:0] *> clk_b 01 Posedge (Const(1.0)))
	SETUP(addr_b[4:0] *> clk_b 10 Posedge (Const(1.0)))
	SETUP(di_b[31:0] *> clk_b 01 Posedge (Const(0.5)))
	SETUP(di_b[31:0] *> clk_b 10 Posedge (Const(0.5)))
	SETUP(we_b *> clk_b 01 Posedge (Const(0.5)))
	SETUP(we_b *> clk_b 10 Posedge (Const(0.5)))

	HOLD(addr_a[4:0] *> clk_a 01 Posedge (Const(0.5)))
	HOLD(addr_a[4:0] *> clk_a 10 Posedge (Const(0.5)))
	HOLD(addr_b[4:0] *> clk_b 01 Posedge (Const(0.5)))
	HOLD(addr_b[4:0] *> clk_b 10 Posedge (Const(0.5)))
	HOLD(di_b[31:0] *> clk_b 01 Posedge (Const(0.5)))
	HOLD(di_b[31:0] *> clk_b 10 Posedge (Const(0.5)))
	HOLD(we_b *> clk_b 01 Posedge (Const(0.5)))
	HOLD(we_b *> clk_b 10 Posedge (Const(0.5)))
)


Cell(timing_spram_64x14
	PIN(clk
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	
	BUS(addr[5:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di[13:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do[13:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk *> do[13:0] 01 01
		Delay((Const (2.0)))
		Slew((Const(0.3))))
	PATH(clk *> do[13:0] 01 10
		Delay((Const (2.0)))
		Slew((Const(0.3))))

	SETUP(addr[5:0] *> clk 01 Posedge (Const(1.0)))
	SETUP(addr[5:0] *> clk 10 Posedge (Const(1.0)))
	SETUP(di[13:0] *> clk 01 Posedge (Const(0.5)))
	SETUP(di[13:0] *> clk 10 Posedge (Const(0.5)))
	SETUP(we *> clk 01 Posedge (Const(0.5)))
	SETUP(we *> clk 10 Posedge (Const(0.5)))

	HOLD(addr[5:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(addr[5:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(di[13:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(di[13:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(we *> clk 01 Posedge (Const(0.5)))
	HOLD(we *> clk 10 Posedge (Const(0.5)))
)

Cell(timing_spram_64x22
	PIN(clk
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	BUS(addr[5:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di[21:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do[21:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk *> do[21:0] 01 01
		Delay((Const (2.0)))
		Slew((Const(0.3))))
	PATH(clk *> do[21:0] 01 10
		Delay((Const (2.0)))
		Slew((Const(0.3))))

	SETUP(addr[5:0] *> clk 01 Posedge (Const(1.0)))
	SETUP(addr[5:0] *> clk 10 Posedge (Const(1.0)))
	SETUP(di[21:0] *> clk 01 Posedge (Const(0.5)))
	SETUP(di[21:0] *> clk 10 Posedge (Const(0.5)))
	SETUP(we *> clk 01 Posedge (Const(0.5)))
	SETUP(we *> clk 10 Posedge (Const(0.5)))

	HOLD(addr[5:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(addr[5:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(di[21:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(di[21:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(we *> clk 01 Posedge (Const(0.5)))
	HOLD(we *> clk 10 Posedge (Const(0.5)))
)

Cell(timing_spram_64x24
	PIN(clk
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	BUS(addr[5:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di[23:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do[23:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk *> do[23:0] 01 01
		Delay((Const (2.0)))
		Slew((Const(0.3))))
	PATH(clk *> do[23:0] 01 10
		Delay((Const (2.0)))
		Slew((Const(0.3))))

	SETUP(addr[5:0] *> clk 01 Posedge (Const(1.0)))
	SETUP(addr[5:0] *> clk 10 Posedge (Const(1.0)))
	SETUP(di[23:0] *> clk 01 Posedge (Const(0.5)))
	SETUP(di[23:0] *> clk 10 Posedge (Const(0.5)))
	SETUP(we *> clk 01 Posedge (Const(0.5)))
	SETUP(we *> clk 10 Posedge (Const(0.5)))

	HOLD(addr[5:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(addr[5:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(di[23:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(di[23:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(we *> clk 01 Posedge (Const(0.5)))
	HOLD(we *> clk 10 Posedge (Const(0.5)))
)

Cell(timing_1200_spram_1024x8
	PIN(clk
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	
	BUS(addr[9:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di[7:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do[7:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk *> do[7:0] 01 01
		Delay((Const (2.5)))
		Slew((Const(0.3))))
	PATH(clk *> do[7:0] 01 10
		Delay((Const (2.5)))
		Slew((Const(0.3))))

	SETUP(addr[9:0] *> clk 01 Posedge (Const(1.0)))
	SETUP(addr[9:0] *> clk 10 Posedge (Const(1.0)))
	SETUP(di[7:0] *> clk 01 Posedge (Const(0.5)))
	SETUP(di[7:0] *> clk 10 Posedge (Const(0.5)))
	SETUP(we *> clk 01 Posedge (Const(0.5)))
	SETUP(we *> clk 10 Posedge (Const(0.5)))

	HOLD(addr[9:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(addr[9:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(di[7:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(di[7:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(we *> clk 01 Posedge (Const(0.5)))
	HOLD(we *> clk 10 Posedge (Const(0.5)))
)

Cell(timing_1200_spram_1024x32
	PIN(clk
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	
	BUS(addr[9:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di[31:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do[31:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk *> do[31:0] 01 01
		Delay((Const (2.5)))
		Slew((Const(0.3))))
	PATH(clk *> do[31:0] 01 10
		Delay((Const (2.5)))
		Slew((Const(0.3))))

	SETUP(addr[9:0] *> clk 01 Posedge (Const(1.0)))
	SETUP(addr[9:0] *> clk 10 Posedge (Const(1.0)))
	SETUP(di[31:0] *> clk 01 Posedge (Const(0.5)))
	SETUP(di[31:0] *> clk 10 Posedge (Const(0.5)))
	SETUP(we *> clk 01 Posedge (Const(0.5)))
	SETUP(we *> clk 10 Posedge (Const(0.5)))

	HOLD(addr[9:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(addr[9:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(di[31:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(di[31:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(we *> clk 01 Posedge (Const(0.5)))
	HOLD(we *> clk 10 Posedge (Const(0.5)))
)

Cell(timing_1200_spram_2048x8
	PIN(clk
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	
	BUS(addr[10:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di[7:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do[7:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk *> do[7:0] 01 01
		Delay((Const (2.5)))
		Slew((Const(0.3))))
	PATH(clk *> do[7:0] 01 10
		Delay((Const (2.5)))
		Slew((Const(0.3))))

	SETUP(addr[10:0] *> clk 01 Posedge (Const(1.0)))
	SETUP(addr[10:0] *> clk 10 Posedge (Const(1.0)))
	SETUP(di[7:0] *> clk 01 Posedge (Const(0.5)))
	SETUP(di[7:0] *> clk 10 Posedge (Const(0.5)))
	SETUP(we *> clk 01 Posedge (Const(0.5)))
	SETUP(we *> clk 10 Posedge (Const(0.5)))

	HOLD(addr[10:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(addr[10:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(di[7:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(di[7:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(we *> clk 01 Posedge (Const(0.5)))
	HOLD(we *> clk 10 Posedge (Const(0.5)))
)

Cell(timing_spram_2048x32
	PIN(clk
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	
	BUS(addr[10:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di[31:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do[31:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk *> do[31:0] 01 01
		Delay((Const (2.5)))
		Slew((Const(0.3))))
	PATH(clk *> do[31:0] 01 10
		Delay((Const (2.5)))
		Slew((Const(0.3))))

	SETUP(addr[10:0] *> clk 01 Posedge (Const(1.0)))
	SETUP(addr[10:0] *> clk 10 Posedge (Const(1.0)))
	SETUP(di[31:0] *> clk 01 Posedge (Const(0.5)))
	SETUP(di[31:0] *> clk 10 Posedge (Const(0.5)))
	SETUP(we *> clk 01 Posedge (Const(0.5)))
	SETUP(we *> clk 10 Posedge (Const(0.5)))

	HOLD(addr[10:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(addr[10:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(di[31:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(di[31:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(we *> clk 01 Posedge (Const(0.5)))
	HOLD(we *> clk 10 Posedge (Const(0.5)))
)

Cell(timing_spram_256x21
	PIN(clk
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	
	BUS(addr[7:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di[20:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do[20:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk *> do[20:0] 01 01
		Delay((Const (2.0)))
		Slew((Const(0.3))))
	PATH(clk *> do[20:0] 01 10
		Delay((Const (2.0)))
		Slew((Const(0.3))))

	SETUP(addr[7:0] *> clk 01 Posedge (Const(1.0)))
	SETUP(addr[7:0] *> clk 10 Posedge (Const(1.0)))
	SETUP(di[20:0] *> clk 01 Posedge (Const(0.5)))
	SETUP(di[20:0] *> clk 10 Posedge (Const(0.5)))
	SETUP(we *> clk 01 Posedge (Const(0.5)))
	SETUP(we *> clk 10 Posedge (Const(0.5)))

	HOLD(addr[7:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(addr[7:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(di[20:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(di[20:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(we *> clk 01 Posedge (Const(0.5)))
	HOLD(we *> clk 10 Posedge (Const(0.5)))
)

Cell(timing_spram_512x20
	PIN(clk
		PINTYPE(input)
		CLOCK_PIN
		CAPACITANCE(0.5)
	)
	
	BUS(addr[8:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(di[19:0]
		BUSTYPE(input)
		CAPACITANCE(0.5)
	)
	BUS(do[19:0]
		BUSTYPE(output)
		CAPACITANCE(0.5)
	)
	PIN(we
		PINTYPE(input)
		CAPACITANCE(0.5)
	)
	PATH(clk *> do[19:0] 01 01
		Delay((Const (2.0)))
		Slew((Const(0.3))))
	PATH(clk *> do[19:0] 01 10
		Delay((Const (2.0)))
		Slew((Const(0.3))))

	SETUP(addr[8:0] *> clk 01 Posedge (Const(1.0)))
	SETUP(addr[8:0] *> clk 10 Posedge (Const(1.0)))
	SETUP(di[19:0] *> clk 01 Posedge (Const(0.5)))
	SETUP(di[19:0] *> clk 10 Posedge (Const(0.5)))
	SETUP(we *> clk 01 Posedge (Const(0.5)))
	SETUP(we *> clk 10 Posedge (Const(0.5)))

	HOLD(addr[8:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(addr[8:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(di[19:0] *> clk 01 Posedge (Const(0.5)))
	HOLD(di[19:0] *> clk 10 Posedge (Const(0.5)))
	HOLD(we *> clk 01 Posedge (Const(0.5)))
	HOLD(we *> clk 10 Posedge (Const(0.5)))
)

References:
- Re: [openrisc] generic flip-flop based memories.
  - From: "Damjan Lampret" <lampret@opencores.org>

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