Hi Marko,
Thanks for your quick response to my question. But what I meant in my original message is in ATS only 19 test cases are intentionally checked while the rest 7 test cases are left unchecked in or1ksim/testbench. I think I got the correct tools for running those 7 test cases, but they failed because "bus error" except occurs. In the Makefile, the test cases "mc_dram", "mc_ssram", "mc_sync" and "mc_async" are built using link file "default.ld" which may not be good for them. Please help to check if this is cause. Thanks!
Dennis
Marko Mlinar <markom@opencores.org> wrote:
Dennis,
for a few days tools were broken, it should be ok now.
Please use openrisc mailing list for openrisc related issues.
Marko
On Tuesday 04 March 2003 08:36, you wrote:
> Hi,
> ATS only runs 19 test cases out of 26 total in /or1ksim/testbench. I
> tried to run the rest of them (eg., mc_dram), but failed. I used the
> default simulation configuration file "default.cfg". "bus error" except was
> generated in the simulation. Please help point out what's cause for it.
> Thanks,
>
> Dennis