Re: [openrisc] Cell not translated

[Richard Herveille <richard@asics.ws>]

This is a synthesizer warning that it cannot instantiate the ramblocks. 
Apparantly OpenRISC is currently configured for Xilinx memories. Replace the 
blocks with your FPGA vendor's equivalent of Xilinx' RAMB4_16. Altera for 
example has direct replacements for them.
And yes OR1200 is synthesizable, it's running on my board.

Richard


> Hi, All,
>
> I want to use OpenRisc as the netlist for my project. When I try to compile
> and synthsis, there is warning:
>
> Warning: Cell 'or1200_immu_top/or1200_immu_tlb/itlb_mr_ram/ramb4_s16_0'
> (RAMB4_S16) not translated. (TRANS-1) Warning: Cell
> 'or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/ramb4_s16_0' (RAMB4_S16_1) not
> translated. (TRANS-1) Warning: Cell
> 'or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/ramb4_s16_1'
> (RAMB4_S16_param_1) not translated. (TRANS-1) Warning: Cell
> 'or1200_ic_top/or1200_ic_ram/ic_ram0/ramb4_s4_0' (RAMB4_S4) not translated.
> (TRANS-1) Warning: Cell 'or1200_ic_top/or1200_ic_ram/ic_ram0/ramb4_s4_1'
> (RAMB4_S4_param_1) not translated. (TRANS-1) Warning: Cell
> 'or1200_ic_top/or1200_ic_ram/ic_ram0/ramb4_s4_2' (RAMB4_S4_param_2) not
> translated. ......
>
> Anyone can tell me why and how to make it synthsizable?
>
> Is OpenRisc1200 synthsizable?
>
> Thanks in advance.
>
> Lei

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