Re: [openrisc] Caches lock and invalidate

[Javier <javier@teisa.unican.es>]

  After think about this I believe is good idea to perform a miss and write 
the block into the cache.I  This is because if the cache invalidate is 
implemented, the block lock have to do (more or less) the same funcionality 
so no extra logic is needed.

Regards

Javier Castillo

On Friday 24 January 2003 10:54, Damjan Lampret wrote:
> Good question. It is not defined right now what happens. So as it is right
> now, it would be implementation specific what happens.
>
> regards,
> Damjan
>
> ----- Original Message -----
> From: <javier@teisa.unican.es>
> To: <openrisc@opencores.org>
> Sent: Friday, January 24, 2003 1:17 PM
> Subject: [openrisc] Caches lock and invalidate
>
> > Hi:
> >
> >    I hava a question about the cache block lock and cache invalidate.
> > Suppose you have a cache memory with 2 ways. If you perform a cache
> > lock or invalidate of a effective address you must read first if that
> > efective address is in the cache. If the block is in the cache you
> > lock/invalidate it. But when the EA is not in cache memory what
> > happens? The block lock is discarded or a miss occurs and the block is
> > prefetched to cache memory and then locked.
> >
> >   Thanks
> >
> > --
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