[openrisc] Instruction code...

[Manuk Shemsyan <s_manuk@freenet.am>]

Hello lampret,

Monday, January 6, 2003, 2:45:38 PM, you wrote:

loo> Heya !

loo> For general understanding I want to make something clear. Cached and 
loo> uncached areas should not be specified by architecture of the 
loo> processor, but rather by system architecture. This is the reason why 
loo> ORP as an example of reference system specifies what address space is 
loo> cached and what not (usually cached is where peripherals are).

loo> or1k architecture does specify that you can use MMU (via PTEs) to 
loo> cache or uncache certain address spaces. However it doesn't specify 
loo> how to cache/uncache address spaces if there is no MMU. Conclusion 
loo> would be that implementation can chose its own way how to specify 
loo> cached/uncached areas. For example if you look at or1200 you will see 
loo> that if MMU is not impemented, you have a define that defines which 
loo> areas will be cached and which not. See or1200_defines.v.

loo> regards,
loo> Damjan

loo> ----- Original Message ----- 
loo> From: Marķa Bolado <mbolado@t... > 
loo> To: "OpenRisc Forum" <openrisc@o... > 
loo> Date: Wed, 20 Nov 2002 12:22:48 +0100 
loo> Subject: [openrisc] Non-cacheable sectors 

>> Hello again! 
>> If you have an OR1000 implementation without virtual memory 
>> (without MMU), how can you define non-cacheable memory sectors? 
>> Aparently, the only way to define non-cacheable sectors is using 
Hi everybody,
I am looking for documentation of AVR 8 bit MCU instruction code,
suitable for IP Core design.

-- 
Best regards,
 Manuk                            mailto:s_manuk@freenet.am

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