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[openrisc] Interrupt servicing
Hallo!
I've a question about the Programmable Interrupt Controller. As described in
the Architecture Manual, the interrupt line to the CPU rises whenever an
unmasked interrupt line to the PIC comes up, and it remains on active state
until the actual device drops it. The PICSR is like a mirror of the PIC
interrupt input lines.
I'm not really sure, but wouldn't it be better if the interrupt could be
cleared just writting to the PICSR? A very slow device could need a long time
to be accessed, and with current implementation during that time there would
be no way of clearing a interrupt caused by such device. If we could write a
"0" to the correspoding bit in PICSR to make the line go low, interrupt
processing wouldn't be blocked so long. I don't know whether it has any wrong
effects...
It's only an idea, tell me what you think (this is *really* a Request For
Comments ;-) ).
Merry Christmas!
Carlos
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