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Re: [openrisc] Could anybody help with 'full associative cache' topic? Thank you very much.



Heya !
 
Configuration registers are just for telling the low level software how many ways you have in case the software wants to know. Since AFAIK no software uses configuration registers at the moment, you don't even need to implement configuration registers, they are there just for software that might want to use them in the future. I believe that most apps will have much less than 32 ways. If somebody wants to have more, then it should either have to make sure that any third party software doesn't depend on NCW field, or modify the software to only look at version of the RISC instead of configuration registers. But one way is also to define that certain value (like all bits set to 1 perhaps) means undefined number of ways, or number of ways more than defined by "normal" value in the register.
 
regards,
Damjan
----- Original Message -----
Sent: Wednesday, November 13, 2002 4:23 PM
Subject: [openrisc] Could anybody help with 'full associative cache' topic? Thank you very much.

Hello again!
In OR1000 architecture you define a set of configuration registers (i.e. DCCR, ICCR, IMMUCR...). In particular, i am interested in Data Cache Configuration Register.
There is a group of bits NCW (Number of Cache Ways) that allows you to choose among several number of ways, from 1 way to 32 ways. My question is: if I want a full-associative cache in my implementation, how should I set this group of bits? Theoretically, i could not implement a full-associative cache greater than 32 blocks (32 ways with one block per way) but I don't think this would be an appropiate restriction.
Can you help?