Hi,
When cache is enabled, breakpoints can be set in current or1200 implementation (without error)?
According to current implemetation of or1200, Dbg_IF is attatched between main memory and cache memories.
This means that CPU core never meet the l.trap instrucion if the address of l.trap was allocated to I$ already before breakpoint setting.
Another question!
Is the NEXT(or STEP) function of GDB implemented using breakpoint mechanism (setting l.trap)?
Regards,
maunal