Re: [openrisc] DSP instructions assembler error

["xxxx" <meleth_esp@yahoo.es>]

If I use this program:

main(){

   int i,j,k;
   k=4;
   j=7;
   i=5;
   i=i+6;

   __asm__ __volatile__ ("lv.add.b  %0,%1,%2"
        :"=r"(i)
        : "r"(j),"r"(k));

}

It assemble well but with these one
main(){

   int i,j,k;
   k=4;
   j=7;
   i=5;
   i=i+6;

   __asm__ __volatile__ ("lv.cmp_le.b  %0,%1,%2"
        :"=r"(i)
        : "r"(j),"r"(k));

}

I obtain the unknow opcode error.




----- Original Message -----
From: "Marko Mlinar" <markom@opencores.org>
To: <openrisc@opencores.org>
Sent: Monday, September 16, 2002 9:36 AM
Subject: Re: [openrisc] DSP instructions assembler error


> This is not a bug. You used asm directive incorrectly.
> You directly assigned registers to instructions, so gcc treats string
> "lv.add.h  r3,r4,r6" as an instruction. If you would write
"sdsdsagfdht643"
> it would directly copy it to .S file, but in the latter case assembler
would
> complain. You should either use "volatile" keyword, if the instruction
should
> not be moved, or assign registers outside asm keyword, or at least assign
> constrained register to instruction. See gcc manual for more info.
>
> Marko
>
> On Friday 13 September 2002 18:05, Damjan Lampret wrote:
> > This looks like a bug. We need a few days to check out, meanwhile you
can
> > also try to find this bug.
> >
> > regards,
> > Damjan
> >
> > ----- Original Message -----
> > From: <javier_castillo_villar@yahoo.es>
> > To: <openrisc@opencores.org>
> > Sent: Friday, September 13, 2002 8:37 PM
> > Subject: [openrisc] DSP instructions assembler error
> >
> > > I am attempting to assemble dsp instructions with the port of binutils
> > > but when I attemp to assemble a dsp instruction wich contains a _ the
> > > assembler fails.
> > >
> > > For example this program:
> > >
> > > main(){
> > >
> > >    int i;
> > >    i=5;
> > >    i=i+6;
> > >
> > >    asm("lv.add.h  r3,r4,r6");
> > >
> > > }
> > >
> > > with the orden or32-uclinux-gcc -S suma.c generate:
> > >
> > > l.addi   r1,r1,-8
> > > l.sw     0(r1),r2
> > > l.addi   r2,r1,8
> > > l.addi  r3,r0,5 # move immediate
> > > l.sw    -4(r2),r3
> > > l.lwz    r3,-4(r2) # SI load
> > > l.addi  r3,r3,6
> > > l.sw    -4(r2),r3
> > > lv.add.h  r3,r4,r6    ************* THE ORDER IN ASM
> > > l.addi  r11,r3,0 # move reg to reg
> > > l.lwz    r2,0(r1)
> > > l.jr  r9
> > > l.addi   r1,r1,8
> > >
> > > And writing or32-uclinux-as suma.s assemble without errors. If I use a
> > > DSP instruction with a _ like lv.cmp_le.b in this code:
> > >
> > > main(){
> > >
> > >    int i;
> > >    i=5;
> > >    i=i+6;
> > >
> > >    asm("lv.cmp_le.b  r3,r4,r6");
> > >
> > > }
> > >
> > > I obtain a similar result in asm
> > >
> > > l.addi   r1,r1,-8
> > > l.sw     0(r1),r2
> > > l.addi   r2,r1,8
> > > l.addi  r3,r0,5 # move immediate
> > > l.sw    -4(r2),r3
> > > l.lwz    r3,-4(r2) # SI load
> > > l.addi  r3,r3,6
> > > l.sw    -4(r2),r3
> > > lv.cmp_le.b  r3,r4,r6    **************THE ORDER I ADD
> > > l.addi  r11,r3,0 # move reg to reg
> > > l.lwz    r2,0(r1)
> > > l.jr  r9
> > > l.addi   r1,r1,8
> > >
> > >
> > > But when I try to assemble it says:
> > >
> > > suma.s:19 Error: unknow opcode1: 'lv.cmp_le.b r3,r4,r6'
> > >
> > > I look at /binutils/opcodes/or32.c and these instructions are added
to.
> > >
> > >
> > > I attempt to use all the DSP isntructions with an _ in his opcode and
> > > noone assemble but the ones that dont have a _ works well.
> > >
> > >
> > > Is this a bug or maybe I am doing something wrong?
> > >
> > > Thanks
> > >
> > >
> > >
> > > --
> > > To unsubscribe from openrisc mailing list please visit
> >
> > http://www.opencores.org/mailinglists.shtml
>
> --
> To unsubscribe from openrisc mailing list please visit
http://www.opencores.org/mailinglists.shtml

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