Re: [openrisc] OR chip? Free .35 CMOS Foundry Run (fwd)

["Damjan Lampret" <lampret@opencores.org>]

Can be used, but this is good only for engineering samples. And I wonder
what does it mean "free" since these MPW runs are usually a couple of
thousand $ (which is nearly free compared to production run).

regards,
Damjan

----- Original Message -----
From: <oystein@homelien.no>
To: <openrisc@opencores.org>
Sent: Tuesday, May 14, 2002 10:03 PM
Subject: [openrisc] OR chip? Free .35 CMOS Foundry Run (fwd)


> I'm just following opencores from the side lines, trying to learn, but I
> am looking for openrisc 1001 or 1200 implemented in an actual IC. :)
>
> Would offers like this "free engineering run" (see below) be an
> opportunity to get chips made cheap?  Is this the kind of process that
> could be used?
>
> ---------- Forwarded message ----------
> Date: Tue, 14 May 2002 21:28:14 +0200 (CEST)
> From: sales@alphat.com
> To: oystein@socketip.no
> Subject: Free .35 CMOS Foundry Run
>
>
>
> Alpha Technologies Foundry e-Newsletter May '02
>
> In this issue:
> 1) Free Engineering Run on 0.35 um CMOS (deadline May 24)
> 2) New Alpha Wafer Foundry Processes
>
> 1) Free Multi-Product Wafer Run on TSMC Compatible 0.35 um CMOS*
> Deadline for GDS submission is May 24, 2002
> (*quantities limited - first come first served basis)
>
> An Alpha consortium 8 inch wafer fab is offering a FREE 0.35 um TSMC
> compatible CMOS wafer run. This is an opportunity to test a new second
> source fab at no cost.
>
> Please email sales@alphat.com for details, database requirements and to
> apply for space on the multi-product wafer run ("pizza mask")
>
> Process information.
>
> The following TSMC compatible process options can be fabricated on this
> run:
> - 0.35 µm Double Poly, Triple Metal Mixed Signal  Process (Polycide).
> - 0.35 µm Double Poly, Quadruple Metal Mixed Signal  Process (Polycide).
> - 0.35 µm Double Poly, Quadruple Metal, High Resistive Poly Process
> (Polycide)
>
> We will deliver sample dies or packaged samples in plastic or ceramic
> packages
>
> Tape out deadline: gds data must be sent before May 24th
>
> Fab out target date: end of August, 2002
>
> Costs: all listed services are free of charge
>
>
> 2)  New Alpha Wafer Foundry Processes
>
> Alpha Technologies has a new 0.25 um BiCMOS process available for
> foundry customers
>
> View data sheets by clicking on the following links. Visit our site to
> sign-up for free email updates of new processes, models and  cells
>
> 1) 0.25 um BiCMOS
>
> http://www.alphat.com/bicmos_0.25um.shtml
>
> 2) 25 GHz bipolar for linear or high speed logic designs with Photodiode
>
> http://www.alphat.com/bipolar_process_p42b.shtml
>
> 3) Low cost bulk silicon 120 volt BCDMOS
>
> 120 volt BCDMOS webpage under construction, please inquire for details
>
> Alpha Technologies is a wafer foundry consortium for special purpose
> IC processes.  We can install your process or provide design kits
> on our existing processes for your new designs.  Email us at
> sales@alphat.com or call us at 408-934-0100 to discuss your foundry
> and ASIC requirements.
>
>
>
> To unsubscribe from our email process updates, reply with "remove" in
> subject line.
>
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