Re: [openrisc] OR1200 problem

[Shawn Tan <shawn.tan@aeste.net>]

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Damjan Lampret wrote:
| If it is something from Cadence, Mentor or Synopsys, it should
probably work.
|
It's not.. I plan to use VCS to simulate it later.. for now, the netlist
simulation's seem to run fine.. I'm able to execute reads and writes to
the data mem and also jumps.. next, I'll try to test out some arithmetic
and logical instructions.. I noticed that the first instruction is read
twice.. because two reads are made to address 0x100.. is there a reason
for this??

I've got a question.. just to get things right.. I'm currently coding in
machine code (making a dumbROM implementation).. I printed out the
instruction set from the architecture manual.. I'd like to check to make
sure that my technique is correct..

almost everything is done in 16-bit nibbles..

to move data into a register, I use l.movhi first to move the upper
16-bits in and then ORI it with the lower 16-bits.. is this the best way
to move a 32-bit value into a register??

to store into a data mem location, I use a l.movhi to get the upper
16-bits into a register, and then to a l.sw with another 16-bit offset
to move the data from a register to data mem.. a similar way for load
except that I do a l.lwz instruction..

another question about the custom registers group 24-31.. are they
mapped to the data mem bus or are they mapped to internal registers??
Accessing the lower 64Kb is really easy using R0 as the base register
with a 16-bit offset.. it'll be really best to put the configuration
registers for other cores here..

Thanks for all your help..

With Metta,
Shawn Tan.
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