Re: Re: [openrisc] or1ksim testbenches fail

["Marko Mlinar" <markom@opencores.org>]

Yes this could be nice for uart and eth files, but in this particular case,
eth0.rx should already contain test data.

Marko

----- Original Message -----
From: "Damjan Lampret" <lampret@opencores.org>
To: <openrisc@opencores.org>
Sent: Friday, April 05, 2002 3:55 PM
Subject: Re: Re: [openrisc] or1ksim testbenches fail


> Just an idea. Maybe it wouldn't be bad if the .rx files are automatically
created if they don't exist.
>
> regards,
> Damjan
>
> On 05 Apr 2002 11:33 CET you wrote:
>
> > Jeff Hanoch wrote:
> > >
> > > Hello All,
> > >
> > > I am trying to run the or1ksim testbenches and cannot get past the
cache
> > > test.  I am wondering if I am doing something wrong or if there is
> > > something wrong in the testbench.
> > >
> > Yes, there was a bug regarding the linker file that should be used when
> > building cache test. This is now fixed, but you will find out, that eth
> > test will not succeed. The eth0.rx, which provides the test input
> > packets is missing. Ivan will provide this file shortly.
> >
> > Simon
> > --
> > To unsubscribe from openrisc mailing list please visit
http://www.opencores.org/mailinglists.shtml
>
> --
> To unsubscribe from openrisc mailing list please visit
http://www.opencores.org/mailinglists.shtml
>

--
To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml