Re: Re: [openrisc] XSV800

["Marko Mlinar" <markom@opencores.org>]

There is a bit in SR (Status register), accessible via
mfspr/mtspr, which is responsible for interrupt
enabling/disabling.

Marko

----- Original Message -----
From: "xu hu" <giro_cn@yahoo.com>
To: <openrisc@opencores.org>
Sent: Tuesday, April 02, 2002 8:57 AM
Subject: Re: Re: [openrisc] XSV800


> hi Lampret,
>     Thanks for all your help. I have make all of them
> work.:)
>     This morning i look at the instruction set of the
> OR1200, but i find there is not the instruction like
> cli/sti in X86, can you give me some clue about the
> how and why the instruction set is like that?
>     Thanks again.
>
> giro.
> --- Damjan Lampret <lampret@opencores.org> wrote:
> > You can try ordering one at http://www.xess.com.
> >
> > regards,
> > Damjan
> >
> > On 30 Mar 2002 18:04 CET you wrote:
> >
> > > hi Damjan,
> > >     I am willing to be a beta tester for
> > ORP/OP1200,
> > > if i can get a XESS XSV800 board( i can pay for
> > it)!
> > >     some idea?
> > >
> > > giro.
> > >
> > > --- Damjan Lampret <lampret@opencores.org> wrote:
> > > > Hi !
> > > >
> > > > How many people on this forum has an XESS XSV800
> > > > board and is willing to be a beta tester for
> > > > ORP/OR1200?
> > > >
> > > > regards,
> > > > Damjan
> > > >
> > > > --
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