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[openrisc] Re: binutils, gcc and Linux on the OpenRISC [repost]
On Mon, Mar 25, 2002 at 09:05:00AM +0100, Marko Mlinar wrote:
>
> OpenRISC Reference Platform (ORP)
>
> Address Space
>
> 0xf000_0000 - 0xffff_ffff Cached 256MB ROM
> 0xc000_0000 - 0xefff_ffff Cached 768MB Reserved
> 0xb800_0000 - 0xbfff_ffff Uncached 128MB Reserved for custom devices
> 0xa600_0000 - 0xb7ff_ffff Uncached 288MB Reserved
> 0xa500_0000 - 0xa5ff_ffff Uncached 16MB Debug 0-15
> 0xa400_0000 - 0xa4ff_ffff Uncached 16MB Digital Camera Controller 0-15
> 0xa300_0000 - 0xa3ff_ffff Uncached 16MB I2C Controller 0-15
> 0xa200_0000 - 0xa2ff_ffff Uncached 16MB TDM Controller 0-15
[...]
Is that how OR platforms would generally be built? IMHO it's a bad idea
to hardcode the address of every conceivable piece of hardware.
The OS/firmware can discover PCI addresses since it has to set them
itself. Since Wishbone devices are usually wired to fixed addresses
this doesn't directly apply.
A device table should be specified which includes device function,
device ID, address and interrupt line (for function and ID we'd need a
central device registry at OpenCores). That table should be stored at
the beginning of the ROM so that the startup code can load it relative
to itself.
That way the hardware can be wired any way that is useful and, since the
table is separate and independent of the software, you wouldn't have to
inject external files (with device config) into the build process of
your software (e.g. the Linux kernel).
Implementing that in Linux should also be easy since you just define a
new bus and set it up with the device table (all buses in Linux have a
PCI-like interface now, independent of that actual bus type).
--
Andreas Bombe <bombe@informatik.tu-muenchen.de> DSA key 0x04880A44
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