[openrisc] Common memory models integrated into SXP processor

["Sam Gladstone" <samg@t-and-t.com>]

Ok, I have integrated the common verilog memory models into the SXP
processor.
The main location is still the same.
"misc/generic_memories/rtl/verilog/"
Copies are located in the "sxp/ram" directory and inlcude paths are pointed
there.
The integration of the new memories does not change any functionality of the
processor.
(Testbench still runs the test assembly code ok.)

Regards,
  Sam Gladstone


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