Re: [openrisc] three more problems

["Damjan Lampret" <lampret@opencores.org>]

----- Original Message -----
From: <jimmy87@sunplus.com.tw>
To: <lampret@opencores.org>; <openrisc@opencores.org>
Sent: Thursday, June 08, 2000 3:42 PM
Subject: [openrisc] three more problems


>
>
> Hi Damjan,
> I want to pose another two problems about OR1K.
>
> 1. if exception such as overflow(add), divided by zero(div/mod) happens in
the
>     delay slot, then we must let CPU keep one bit like MIPS to show the
> exception
>     is in the delay slot.
>     What do you wanna handle it?

I didn't think about those. I wonder how the or1ksim works in this
conditions. I'll check. ;-)

>
> 2. it seems that external interrupt enable control registers are not
defined
> yet.

One possibility is that we don't specify EIER in the architecture. For the
processor core itself it really isn't necessary. But for the complete
platform it is. So if we don't specify for the processor architecture we
must for the overall platform.

> 3. I don't know if you think the follow suggestions are feasible and
should be
> done.
>     (*). if no MMU, I feel we should define one simple memory
architecture.
>             Such as one region is uncached/kernel mode and one region is
> cached/user mode.
>              one region is cached/kernel mode.

Probably not a bad idea. This could be done with cache control registers.
I'll try to add this.

regards,
Damjan