Re: [openrisc] Huffman encoding operands

["Damjan Lampret" <lampret@opencores.org>]

> Jimmy <jimmy87@sunplus.com.tw> wrote:
> >  [ h.configrC <4-bits> is ] similar to the insn lwpai*/swpai*/etc
> > that uses PAIR (post address increment register).
> > It's a good idea. This specific register still has one problem that
> > we must first use mtsr and do some ALU operations and then mfsr again.
> > So, if we hardcoded it into register file, maybe we don't need to
> > use mtsr/mfsr. But auto address increment is good to our means.
> > Besides, MAC insns have that property, too.
>
> That is a different case.  The register file model of or1k (correct me
> if I'm wrong) is two-read one-write per cycle.  A few instructions,

You are right.
> (autoincrement, mult, div, and mod, maybe more) don't fit with that
> concept.  They need additional hardware registers to support them
> efficiently (alternatively, they could be multi-cycled).

But at least when it comes to autoincrement load/store this is not a
problem. For stores you don't write to register file anything. And loads
usually take at least one additional cycle and you can use this cycle to
update the register used as memory pointer (in the next cycle you write
loaded data to the register file).

Mult, div and mod will take several cycles anyway. Also the idea is to
explicitly request part of that result from a special register (more often
used part is automatically stored in register file). For example lower part
of multiplication is stored in GPR and upper part goes in SPR.

regards,
Damjan