[openrisc] OR1001

["Damjan Lampret" <lampret@opencores.org>]

Folks,

I have put OR1001 VHDL sources in OpenCores CVS. Please bear in mind that
this version is in the middle of modifications to add MIPS I support. Also
OR1001 is different than OR1001 mentioned in EETimes article (that one was
renamed to OR1003 and modified to harvard microarchitecture). Anyway OR1001
takes about 80% of XCV50 and runs at about 85MHz in XCV -6. I know some
optimizations that needs to be done in order to go as high as 112MHz in
XCV -6. According to Xilinx P&R software OR1001 is equal to 19k FPGA gates.
Again, OR1001 is still under development (e.g. superfast context mentioned
in the sources is not yet supported etc.). Also currently GCC is not in sync
with current OR1001 and OR32 ISA.

I plan to put beta architecture manual on the web later tonight (but it is
not finished that's why it is called beta). Anyway I'll publish the URL only
on openrisc mailing list (you can look up in the openrisc mailing list
archive if you are not interested to join the list).

regards, Damjan

PS I won't be able to reply to emails sent directly to me for the next 7
days since I'll be in San Jose in this time. If anyone is interested to meet
me there send me private email in the next 12hrs. I'll have a complete
OCRP-1 with me and some other OpenRISC related material.