[fpu] Add/Sub Unit Test Vectors

["Rudolf Usselmann" <rudi@mozart.inet.co.th>]

Hi !


I have written a Single Precision Pipelined Add/Sub Unit,
(including all normalization blocks). I'm looking for test vectors
to verify it really works correctly and covers all corner cases.
My goal was to make it IEEE 754 compliant. It's not quite complete,
but should be soon. I have written it in Verilog, and will submit
it to open cores, if there is any interest ....

Best Regards,

rudi

rudi@inet.co.th