Re: [ethmac] Internal DMA & Buffer Descriptors

["Jim Dempsey" <tapedisk@ameritech.net>]

Jesse,

Let me first state that I know absolutely nothing in regards to how the
receive portion is actualy done. The following is simply an assumption
so use the information with caution. I believe the interpretation
problem is a result of what is not said..

First thing to understand is regardless of direction of transfer
(Read or Write) the DMA engine's next address register is
written to with the updated address for the next transfer

    NextAddress += 4

Or something like that.

I believe that this is what is meant by the DMA engine writes
the buffer address.

I believe a different interpretation of the information you quoted is

Due to it being unknown prior to the reception of a frame, what
the length of the frame is, you can determine the length of the frame
by comparing the DMA address register after it is written at the
completion of transfer to what it was setup to before the transfer.

 i.e.

    You initialize the Next Address
    receive (partial) packet of unknown length
    compare current Next Address with initial Next Address

A simple test could confirm this.

Jim



----- Original Message -----
From: <kempaj@yahoo.com>
To: <ethmac@opencores.org>
Sent: Tuesday, August 06, 2002 3:25 PM
Subject: [ethmac] Internal DMA & Buffer Descriptors


> Hello,
>
> I am wondering if anyone can be of assistance in a clarification. I
> recently (just a couple weeks ago) downloaded Igor's latest revision of
> the MAC core, and am working on integrating it for use with a soft-core
> CPU (nios) as a research project.
>
> I've managed to sucessfully tie together the core to my logic, and poke
> registers around as well. The next step was to tackle software design,
> and I am about 90% done with a low-level driver that interfaces the
> MAC core to my TCP/IP stack. The last step will, of course, be to
> implement any MII commands for the PHY, but I'm waiting for a board
> we design with a phy on it to come back from fab.
>
> Anyways here is the problem: I understand (I think) how BDs work for
> transmission with internal DMA. I set all the control bits as I wish, set
> the length, and set a pointer to the address in data memory where my
> TCP/IP stack has assembled a packet to send (Wishbone DMA inside of
> Igor's core masters this memory along with my CPU). I give the GO
> command and the frame is transmitted - this is all clear to me.
>
> What is not clear to me is BD operation when receiving frames. In the
> Ethernet IP Core Specification PDF document, page 29 (frame reception)
> states: "The Ethernet IP Core reads the Rx BD...After the whole frame
> has been received and stored to the memory, the receive status and
> the pointer to memory storing the data are written to the BD".
>
> Herein lies my confusion: How does the MAC core and/or DMA know
> where to store the received data???? I thought that the memory
> allocation for the MAC core was only for control registers and buffer
> descriptors, so this would imply that the DMA portion of the MAC
> core "knows" where to store incoming frames into memory... ideally I'd
> like to control the DMA destination from my CPU - i.e. - write a pointer
> of my choice to the Rx BD's frame pointer, and have DMA store the
> frame memory starting at that address whenever a frame comes in.
>
> This way, my software architecture can very easily be designed to scale
> the number of buffer descriptors in use, and statically allocate 1,500
> bytes (per ethernet packet) of memory for each descriptor.
>
> If anyone can clarify the above operation of the Rx BDs, I would be very
> greatful!
>
> Thank you,
>
> Jesse Kempa
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