Re: [ethmac] Ethernet status

["Benjamin Heyne" <bhe@kt.e-technik.uni-dortmund.de>]

Hi !

I have implemented the core (MIIM, Rx and Tx) for an Ethernet measurement
tool in a Xilinx Spartan (XCS30XL). I am not using the Wishbone interface -
The core is using a SHARC DSP LinkPort to connect to the world. So I have
not tested the Wishbone part of the core.

I have ported the parts I am using for my design to VHDL and modified esp.
the Rx and Tx modules to support the LinkPort interface of the SHARC and
certain other features needed for measurement. The basic Rx/Tx routines are
untouched. In my implementation the DSP has to code/decode the MAC adresses,
so I have also removed this parts from the core.

To test the design in the "Real World" a PCB containing some LinkPorts and a
MII Port was made.

As far as I can say the core is working - although I have not yet tested it
in Full Duplex mode.

It was neccessary for the TX MII signals to change on the falling edge of
TxC - otherwise the Transceiver sometimes got the wrong data.

If someone is interested in this design I will place it on an public
download site.

Regards
Benjamin
==============================================================
Lehrstuhl fuer Kommunikationstechnik,Universitaet Dortmund
Otto-Hahn-Strasse 4, 44227 Dortmund, Germany
Tel: ++49-231-755-3195, Fax: ++49-231-755-3196
www.kt.e-technik.uni-dortmund.de, Raum P1-03-212


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