[ethmac] Ethernet MAC DMA

[bryfos@adaptivemicro.com]

Hi all:

I'm having a lot of difficulty trying to understand the DMA section of the 
core and how one can actually send and receive Ethernet packets.  I've 
been able to compile the core and simulate the MDIO and register 
interfaces in Max-Plus but it is unclear as to how I store data in the 
core to eventually be transmitted and how I know when data has 
already been stored for received packets.  I read the core spec. and it 
refers to the OpenCores DMA/Bridge IP which was no help either.  The 
documentation appears to out of date and I tried the test bench and it 
didn't seem to transmit or receive packets either.  I'm a VHDL guy, so 
reading through the Verilog code has been rough.

Any help or pointers would be greatly appreciated.  Has anybody 
simulated this in Max-Plus???

Thanks,
Bryan 
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