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Re: [ethmac] some improvement



Hi,

   I must missed something, what do you mean by 1-1 and 0-0 ?

of course you need to check the whole nibble one after the other to
detrmine when the preamble and sfd occur to know when the packet start.

also I suggest to add to the mac a page with link that member find while
they surf that are concern this issue, so later on pther can find this
infomation quickly.

lastly about the fifo in the input you don't need to design a "full async
fifo" as there are few thing that you know and can make it simpler, for
example the clock are the same so the only issue is the PPM, than you max
length of a packet is also determined so knowing this and the max PPM you
can tell the depth of the fifo.

have a nice day

   Illan

At 11:31 PM 07/06/2000 +0700, you wrote:
>hi, sorry i'm late.
>thank you Illan for your questions, we made some changes and hope that the
>diagram can help us to make some discussions.
>
>preamble has patern as 10101010 per byte (for 7 bytes) and SFD has
>patern as 10101011. if SFD detector find the 1-1, bits after it will be
>written in receive buffer (work as small fifo). if SFD detector find 0-0,
>there must be an error and the process terminated.
>do we have to check that the paterns before 1-1 are 101010...or just
>consider bit number 6 and 7(and also for 0-0) ?
>
>is there another consideration when we move byte from receive buffer to
>FIFO beside to synchronize with host system clock? (i mean the time
>interval after the first byte written to receive buffer and it move to
>FIFO)
>
>i'm still trying to understand the details of the receive operations for
>half and full duplex, as you can see the signals in diagrams are not
>complete yet.
>
>