Re: [ethmac] first topics

[Kent Dahlgren <kent@praesum.com>]

At 05:35 PM 4/11/00 -0400, you wrote:
>Novan Hartadi wrote:
> > On Fri, 7 Apr 2000, Jeff Garzik wrote:
> > > My suggestion for an architecture:
>
> > > All 32-bit registers.
> > > Command buffered.
> > > Variable receive and transmit descriptor lists and frame sizes.
>
> > Does these descriptors manage frame in transmit and receive FIFO ?
>
>With the RTL-8139 chip, there is a separate transmit and receive FIFO,
>and data is spilled from the FIFO into the descriptors (or ring
>buffer).  I'm not sure about Tulip, I would presume some sort of on-chip
>FIFO, however small, before data gets tossed into the buffers residing
>in main memory via a DMA burst.

That's pretty much how they all work, the FIFO's are to improve efficiency
by giving the ability to do burst transfers, and to deal with bus latency.

Kent
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