[ecc] RE: your question

[Phil Chien <phil@mosart.com.tw>]

Hi, 

Those two codes are of the same if you use Synopsys DC.
But I have the experience your style may not work when I used VHDL in Altera
Maxplus2. Even though, you could first synthesize by DC and write out EDIF
netlist, then
feed to Altera.

It's better style to use "if - else if - else". But if you can guarentee
your code and use
the right tool, you could save the time to change them. If I were you,  I
will try to synthesize it
and compare the result first.

By the way, if you are making IP, you'd better change that.

regards,
Phil

-----Original Message-----
From: zhu.xiangyang@mail.zte.com.cn
[mailto:zhu.xiangyang@mail.zte.com.cn]
Sent: Monday, October 09, 2000 1:59 PM
To: ecc@opencores.org
Subject: 

Hello everyone:
    I am a new comer to this mailinglist(so i have no any contribution to
opencore :( ).
Because i have been engaged in IC design only for a short time, there are
some
question
puzzling me. I am using Verilog HDL. During my coding someone inspected my
code
and told
me there are probably some problems in my code.
    My code is illustrated as follows:

 module(clk, reset, y, a, b, sel_a, sel_b);
   input clk, reset, a, b, sel_a, sel_b;
   output y;
   reg y;
   always@(posedge clk or negedge reset)
     begin
     if(reset)
       y <= 0;
      else
        begin
    //////////////
        if(sel_a)
          y <= a;
        if(sel_b)
          y <= b;
    /////////////
        end
     end
 endmodule

The inspector told me i should do as below:
 ////////////
     if(sel_b)
       y <= b;
     else if(sel_a)
       y <= a;
 ////////////
He said if i do as i like pre-synthesis simulation and post-synthesis
may be diffenent, because different synthesis tools may interpret it
differently. He demanded me to change my code. If i have to change my
code it will be a disaster, because i  have writen about 4,000 lines
of code using the same structer.

Must i change my code? Please help me.