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[cvs-checkins] dbg_interface/rtl/verilog dbg_registers.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] dbg_interface/rtl/verilog dbg_registers.v
From: OpenCores CVS Agent <cvs@www.opencores.org>
Date: Thu, 31 Jul 2003 15:43:42 +0200
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	dbg_interface
Changes by:	simons	03/07/31 15:43:41

Modified files:
	rtl/verilog    : dbg_registers.v 

Log message:
	Reset value for riscsel register set to 1.

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