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[cvs-checkins] spi/ ench/verilog/spi_slave_model.v ench/veril ...

CVSROOT:	/home/oc/cvs
Module name:	spi
Changes by:	simons	03/03/26 15:00:17

Modified files:
	bench/verilog  : spi_slave_model.v tb_spi_top.v 
	doc            : spi.pdf 
	doc/src        : spi.doc 
	rtl/verilog    : spi_defines.v spi_top.v 

Log message:
	Automatic slave select signal generation added.

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