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[cvs-checkins] can/rtl/verilog can_bsp.v

CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	03/02/19 23:26:10

Modified files:
	rtl/verilog    : can_bsp.v 

Log message:
	When a dominant bit was detected at the third bit of the intermission and
	node had a message to transmit, bit_stuff error could occur. Fixed.

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