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[cvs-checkins] can/ ench/verilog/can_testbench.v tl/verilog/c ...

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] can/ ench/verilog/can_testbench.v tl/verilog/c ...
From: OpenCores CVS Agent <cvs@www.lampret.com>
Date: Thu, 9 Jan 2003 20:54:54 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	can
Changes by:	mohor	03/01/09 20:54:54

Modified files:
	bench/verilog  : can_testbench.v 
	rtl/verilog    : can_bsp.v can_fifo.v can_top.v 
	sim/rtl_sim/run: wave.do 

Log message:
	rx fifo added. Not 100 % verified, yet.

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