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[cvs-checkins] pci/rtl/verilog fifo_control.v pciw_fifo_contr ...

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/11/27 19:37:14

Modified files:
	rtl/verilog    : fifo_control.v pciw_fifo_control.v 
	                 wbr_fifo_control.v wbw_fifo_control.v 

Log message:
	Changed the code a bit to make it more readable.
	Functionality not changed in any way.
	More robust synchronization in fifos is still pending.

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