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[cvs-checkins] ac97_ctrl/rtl/verilog ac97_in_fifo.v



CVSROOT:	/home/oc/cvs
Module name:	ac97_ctrl
Changes by:	rudi	02/11/14 16:10:12

Modified files:
	rtl/verilog    : ac97_in_fifo.v 

Log message:
	Fixed a bug in the IN-FIFO - 18 bit samples where not alligned correctly.

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