[cvs-checkins] or1k/orp/orp_soc/rtl/verilog/or1200 or1200_alu ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	02/09/03 21:28:32

Modified files:
	orp/orp_soc/rtl/verilog/or1200: or1200_alu.v or1200_defines.v 
	                                or1200_except.v or1200_mem2reg.v 
	                                or1200_rfram_generic.v 

Log message:
	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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