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[cvs-checkins] or1k/orp/orp_soc/rtl/verilog/or1200 or1200_def ...

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	02/08/22 01:19:00

Modified files:
	orp/orp_soc/rtl/verilog/or1200: or1200_defines.v or1200_sb.v 
	                                or1200_sb_fifo.v 

Log message:
	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
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