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[cvs-checkins] ethernet/rtl/verilog eth_registers.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_registers.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Fri, 16 Aug 2002 21:14:23 -0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/08/16 21:14:23

Modified files:
	rtl/verilog    : eth_registers.v 

Log message:
	Synchronous reset added to all registers. Defines used for width. r_MiiMRst
	changed from bit position 10 to 9.
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