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[cvs-checkins] uart16550/rtl/verilog raminfr.v uart_debug_if. ...

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	02/07/29 20:16:19

Modified files:
	rtl/verilog    : raminfr.v uart_debug_if.v uart_receiver.v 
	                 uart_regs.v uart_rfifo.v uart_tfifo.v 
	                 uart_top.v uart_transmitter.v uart_wb.v 

Log message:
	The uart_defines.v file is included again in sources.
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