[cvs-checkins] ethernet/rtl/verilog eth_wishbone.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/07/25 17:29:02

Modified files:
	rtl/verilog    : eth_wishbone.v 

Log message:
	WriteRxDataToMemory signal changed so end of frame (when last word is
	written to fifo) is changed.
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