CVSROOT: /home/oc/cvs Module name: or1k Changes by: lampret 02/03/29 17:40:10 Modified files: xess/xsv_fpga/orp_soc/rtl/verilog/or1200: or1200_alu.v Log message: Added a directive to ignore signed division variables that are only used in simulation. -- To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml