[cvs-checkins] ac97_ctrl/ ench/verilog/test_bench_top.v ench/ ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ac97_ctrl
Changes by:	rudi	02/03/05 05:44:06

Modified files:
	bench/verilog  : test_bench_top.v tests.v 
	rtl/verilog    : ac97_cra.v ac97_defines.v ac97_dma_if.v 
	                 ac97_dma_req.v ac97_fifo_ctrl.v ac97_in_fifo.v 
	                 ac97_int.v ac97_out_fifo.v ac97_prc.v ac97_rf.v 
	                 ac97_soc.v ac97_top.v ac97_wb_if.v 
	sim/rtl_sim/bin: Makefile 
	sim/rtl_sim/run: Makefile 

Log message:
	- Fixed the order of the thrash hold bits to match the spec.
	- Many minor synthesis cleanup items ...

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