[cvs-checkins] ata/rtl/verilog/ocidec-2 ud_cnt.v timescale.v ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	ata
Changes by:	rherveille	02/02/18 15:27:00

Added files:
	rtl/verilog/ocidec-2: ud_cnt.v timescale.v ro_cnt.v 
	                      revision_history.txt atahost_wb_slave.v 
	                      atahost_top.v atahost_pio_tctrl.v 
	                      atahost_pio_actrl.v atahost_controller.v 

Log message:
	Initial Verilog HDL release

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