[cvs-checkins] mem_ctrl/rtl/verilog mc_mem_if.v mc_obct_top.v ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	mem_ctrl
Changes by:	rudi	01/12/21 06:09:36

Modified files:
	rtl/verilog    : mc_mem_if.v mc_obct_top.v mc_rf.v mc_timing.v 
	                 mc_top.v 

Log message:
	- Fixed combinatorial loops in synthesis
	- Fixed byte select bug

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