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[cvs-checkins] uart16550/rtl/verilog uart_debug_if.v



CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/12/04 22:14:20

Added files:
	rtl/verilog    : uart_debug_if.v 

Log message:
	committed the debug interface file

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