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[cvs-checkins] or1k/mp3/rtl/verilog/or1200 generic_spram_512x20.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] or1k/mp3/rtl/verilog/or1200 generic_spram_512x20.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Tue, 20 Nov 2001 22:26:49 +0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	01/11/20 22:26:49

Modified files:
	mp3/rtl/verilog/or1200: generic_spram_512x20.v 

Log message:
	Fixed virtual silicon single-port rams instantiation.

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