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[cvs-checkins] uart16550/rtl/verilog uart_receiver.v uart_regs.v



CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/11/10 13:43:22

Modified files:
	rtl/verilog    : uart_receiver.v uart_regs.v 

Log message:
	Synthesis bugs fixed. Some other minor changes

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