[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] wb_prefetch_spram/bench/verilog tb_tasks.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] wb_prefetch_spram/bench/verilog tb_tasks.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Thu, 18 Oct 2001 19:40:47 +0200
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	wb_prefetch_spram
Changes by:	lampret	01/10/18 19:40:47

Modified files:
	bench/verilog  : tb_tasks.v 

Log message:
	Added test case for same location R/W/R sequence. Checks for broken SRAMs.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml

Prev by Date: [cvs-checkins] rtc/rtl/verilog rtc_top.v
Next by Date: [cvs-checkins] wb_prefetch_spram/rtl/verilog generic_spram.v
Prev by thread: [cvs-checkins] wb_prefetch_spram/rtl/verilog generic_spram.v
Next by thread: [cvs-checkins] rtc/rtl/verilog rtc_top.v
Index(es):
- Date
- Thread