[cvs-checkins] vga_lcd/rtl/verilog vga_wb_slave.v vga_wb_mast ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	vga_lcd
Changes by:	rherveille	01/10/16 11:07:57

Modified files:
	rtl/verilog    : vga_wb_slave.v vga_wb_master.v vga_vtim.v 
	                 vga_top.v vga_fifo.v vga_csm_pb.v vga_colproc.v 
	                 ro_cnt.v generic_spram.v generic_dpram.v 
Added files:
	rtl/verilog    : vga_defines.v 
Removed files:
	rtl/verilog    : vga_vga_and_clut_top.v 

Log message:
	Major revisions throughout the core.
	Moved Color Lookup Table inside core.
	Changed control & status register contents.
	Changed port names to be conform to new naming convention.
	Fixed bug in CAB assertion.
	Changed video memory address generation.
	and many more ....

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