[cvs-checkins] or1k/or1200/rtl alu.v cfgr.v cpu.v dc.v dc_fsm ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	or1k
Changes by:	lampret	01/09/23 06:50:09

Modified files:
	or1200/rtl     : alu.v cfgr.v cpu.v dc.v dc_fsm.v dc_ram.v 
	                 dc_tag.v defines.v dmmu.v dtlb.v except.v 
	                 frz_logic.v generic_dpram_32x32.v 
	                 generic_spram_2048x32.v generic_spram_2048x8.v 
	                 generic_spram_512x19.v generic_spram_512x20.v 
	                 generic_spram_64x14.v generic_spram_64x21.v 
	                 generic_spram_64x23.v generic_spram_64x37.v 
	                 generic_tpram_32x32.v ic.v ic_fsm.v ic_ram.v 
	                 ic_tag.v id.v ifetch.v immu.v itlb.v lsu.v 
	                 mem2reg.v multp2_32x32.v operandmuxes.v 
	                 or1200.v pic.v pm.v reg2mem.v rf.v sprs.v tt.v 
	                 wb_biu.v wbmux.v xcv_ram32x8d.v 
Added files:
	or1200/rtl     : du.v 

Log message:
	Adding debug capabilities. Half done.

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