[cvs-checkins] uart16550/rtl/verilog timescale.v uart_defines ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	mohor	01/08/23 17:44:35

Added files:
	rtl/verilog    : timescale.v uart_defines.v uart_fifo.v 
	                 uart_receiver.v uart_regs.v uart_top.v 
	                 uart_transmitter.v uart_wb.v 

Log message:
	Stop bit bug fixed.
	Parity bug fixed.
	WISHBONE read cycle bug fixed,
	OE indicator (Overrun Error) bug fixed.
	PE indicator (Parity Error) bug fixed.
	Register read bug fixed.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml