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[cvs-checkins] mem_ctrl/verilog mc_mem_if.v mc_timing.v

CVSROOT:	/home/oc/cvs
Module name:	mem_ctrl
Changes by:	rudi	01/06/14 03:57:37

Modified files:
	verilog        : mc_mem_if.v mc_timing.v 

Log message:
	Fixed a potential bug in a corner case situation where the TMS register
	does not propegate properly during initialisation.

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