head 1.1; branch 1.1.1; access; symbols arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.1 date 2005.04.23.00.39.05; author tak.sugawara; state Exp; branches 1.1.1.1; next ; commitid 1113426998c94567; 1.1.1.1 date 2005.04.23.00.39.05; author tak.sugawara; state Exp; branches; next ; commitid 1113426998c94567; desc @@ 1.1 log @Initial revision @ text @

6 Post-Layout Gate Simulation
6.1 Spartan3 Gate Simulation

Memory Collision Errors are frequently reported as follows.



Since this messages are meaningless for YACC. I checked disable warning option in coregen generation. However situation was the same. There is no help for it , I changed primitive description temporally as follows.

parameter SIM_COLLISION_CHECK = "NONE";//All ORIG TAK Apr.12.2005



Note:
 SDF Error Messages are due to transitional state of simulator at initial power on sequence.




6.2 Stratix2

Run Test Bench at 165MHz.



6.3 Cyclone

Run test bench at 104MHz

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